This invention concerns solid state imagers and image capture systems, and in particular is directed to an improved configuration of the pixels into offset or staggered arrangements of two or more series of pixels. The invention is more particularly concerned with a configuration that employs two or more imager chips butted end-to-end, and which avoids undesirable gain variations from chip to chip. The invention is desirably carried out using low-power CMOS imager technology and offset series of pixels.
Solid state image sensors are used in a wide variety of applications, and there has been much interest in pursuing low-cost, high-resolution, high-reliability image sensors for such applications. CMOS imager technology is advantageous because of the requirement for a only a single power supply voltage, its ruggedness, and its inherent low power consumption. There has been great interest in achieving extremely high resolution also, which requires increased pixel density.
Scanning systems are used for a variety of image capture applications, such as web inspection and document copying and archiving. Conventionally, scanners of this type have utilized either Contact image Sensor (CIS) modules or CCDs to capture the image information. In such scanning systems, CCD imagers are limited in size to only a fraction of the width of the object being scanned, such as a photograph or text. This size limitation arises because of charge transfer difficulties over large distances, i.e., over distances comparable to the width of a page. This requires focusing the image of the document to reduce it down to the size of the imager. While it might be desirable to join a number of CCD imagers end to end to create in effect a single long image capture device, there are many drawbacks that make that impractical.
FIG. 1 illustrates a prior-art scanner arrangement or scanning system 10 which employs a CCD solid state imager 12. A focusing lens system 14 is positioned to focus onto the CCD imager 12 a reduced image of the object, e.g., a sheet of text 16, which is to be scanned. Mirrors (not shown here) may be employed in many practical scanner arrangements. An output buffer 18 is coupled to the CCD imager 12 and is employed via a flexible cable to drive an application-specific integrated circuit (ASIC) 22. An input buffer 20 is also coupled to the CCD imager 12 and is used to interface the captured image data, digitized by an analog-to-digital converter (A/D), to the host computer, networks, or other peripheral devices such as printers or modems, or in some cases all or some portion of a Multi-Function Peripheral (MFP) with image processing functions, motor control, light control, sheet feeder, and user interface ASIC device(s). A desktop system also contains a motor and a light source to move the imager underneath the document 16 to be scanned. Various different light sources such as fluorescent tubes and LEDs, and various different drive motors, such as stepping motors and synchronous motors can be employed. These are well known and not shown here, but would be understood to be included in the scanner system. The CCD imagers have many drawbacks and limitations, such as speed limitations, which arise due to charge transfer efficiency limitations, as well as a high power consumption, and a severely limited capability for integration of other functions onto the pixel array. In addition, in CCD imagers the pixels must be read out in a fixed sequence, which does not permit pixel information to be skipped.
A conventional CIS-based scanning system 30 is illustrated in FIG. 2. In this system, there are a plurality of CIS modules 32(1) to 32(N) joined end to end. The CIS modules 32(1)–32(N) are located in tight proximity to each other to construct a long contiguous array of sensors as wide as the image being captured. An optical coupler 34 is positioned to face the object 36 to be scanned and to focus an image of it onto the array of CIS modules. Because the array of modules 32(1)–32(N) need to be as wide as the object 36 to be scanned, the array has to be quite large. Accurate placement of the CIS modules 32(1)–32(N), which is necessary to pick up the entire image without gaps or jumps across the width of the object, makes the construction of the CIS-based system rather expensive. Also, the various individual CIS sensors each have individual voltage offsets that have to be corrected, and this also adds to the complexity of the system.
An active column sensor (ACS) architecture has recently been developed, as disclosed in Pace et al. U.S. Pat. No. 6,084,229, which permits a CMOS image sensor to be constructed as a single-chip video camera with a performance equal to or better than that which may be achieved by CCD or CID imagers. ACS imagers enjoy very low fixed pattern noise. The principles as disclosed and illustrated in the Pace et al. patent can be advantageously incorporated into imagers employed in scanning applications, and that patent is incorporated herein by reference.